The prior art is replete with different techniques and processes for fabricating semiconductor devices such as metal oxide semiconductor (MOS) transistors. In accordance with typical fabrication techniques, a MOS transistor is formed by creating a device structure on a semiconductor substrate, where the device structure includes a gate stack formed on a layer of semiconductor material, and source and drain regions formed in the semiconductor material to define a channel region under the gate stack. Some transistor devices are intentionally fabricated with asymmetric characteristics to improve their performance. For example, a known fabrication process results in asymmetric extension and/or halo implants in the source and drain regions. In particular, the extension implant in the source region extends further toward or into the channel region, relative to the extension implant in the drain region. Moreover, it may be desirable to use halo implants only in the source region. Such asymmetric fabrication techniques can result in better DC performance (reduction in parasitic resistance, improved mobility, etc.) and better AC performance (less Miller capacitance at the drain side, less junction capacitance at the drain side, etc.). In turn, the power and speed characteristics of the transistor device are improved.
Asymmetric extension and halo implants are typically created using photolithographic techniques, angled ion implantation, and related process steps. Unfortunately, existing photolithography tools are not suitable for modern small-scale process node technology, e.g., 32 nm or 22 nm nodes, which can be used to create gate structures having a pitch of only 130 nm or less. Asymmetric extension and/or halo implants are very difficult (if not impossible) to create in transistor devices fabricated using 32 nm node technology because the narrow gate pitch, photoresist height restrictions, photoresist feature tolerances, ion implantation tilt angle, and other factors introduce geometric limitations that prevent the desired implantation profiles.